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Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication

Contributor(s): Shen, Jih-Sheng (Editor), Hsiung, Pao-Ann (Editor)

ISBN: 9781615208074

Publisher: Igi Global Scientific Publishing

Hardcover
$180.00
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Pub Date: June 30, 2010

Dewey: 621.381531

LCCN: 2009052397

Lexile Code: 0000

Features: Bibliography, Index, Table of Contents

Target Age Group: NA to NA

Physical Info: 1.10" H x 11.20" L x 8.70" W ( 2.85 lbs) 386 pages

Series: Premier Reference Source

Descriptions, Reviews, etc.

Description: Reconfigurable computing brings immense flexibility to on-chip processing while network-on-chip has improved flexibility in on-chip communication. Integrating these two areas of research reaps the benefits of both and represents the promising future of multiprocessor systems-on-chip. Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication is the one of the first compilations written to demonstrate this future for network -on-chip design. Through dynamic and creative research into questions ranging from integrating reconfigurable computing techniques, to task assigning, scheduling and arrival, to designing an operating system to take advantage of the computing and communication flexibilities brought about by run-time reconfiguration and network-on-chip, this book represents a complete source of the techniques and applications for reconfigurable network-on-chip necessary for understanding of future of this field.

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